Structure and method of making an enhanced surface area capacitor

ABSTRACT

A method of making a capacitor structure having an enhanced plate surface area is provided. In such method, a mandrel is provided which has a major surface having an array of features including at least one of: a plurality of first features protruding upward or a plurality of second features extending downward from said surface. A conformal first conductive layer is formed over the mandrel, the first conductive layer conforming to contours of the major surface. A conformal capacitor dielectric layer is formed over the conformal first conductive layer. When the capacitor is an electrolytic capacitor, the conformal capacitor dielectric layer is contacted by an electrolyte. When the capacitor is a plate capacitor, a second plate including a second conformal conductive layer is formed over the conformal capacitor dielectric layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. application Ser. No.10/639,086, filed on Aug. 12, 2003, the disclosure of which isincorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to capacitors and fabrication methodstherefor.

BACKGROUND OF THE INVENTION

In microelectronics manufacturing today, more function is being packedinto ever smaller spaces, often with attendant increases in operationalspeed, and power consumption per unit volume. In addition, someintegrated circuits are being manufactured at much larger die sizes thanonly a few years ago. At such higher speeds, higher power consumption,and larger sizes, relatively large value capacitors are needed in smallspaces to satisfy what can be quite local needs, such as for decouplingof signals on the integrated circuit chip, and decoupling of signalstransferred onto and off of the chip. Moreover, it is desirable tolocate capacitors as close as possible to the sites they are needed,because the conductors which connect capacitors to the sites of interesthave inductance, which can provide significant impedance to counteractthe capacitor action at frequencies of interest. In such environment, ithas become important to provide a small-size, large value capacitor forplacement as near as possible to the site requiring the capacitance, tofacilitate operation of integrated circuits and associated circuitry,including integrated circuit packaging and printed circuit boards.

A diagram illustrating a simple plate capacitor is provided in FIG. 1A.It is known that the capacitance C of a capacitor having two parallelconductive plates 1 and 2 of the same size is determined by the equationC=K*A/dwhere A is the area of one of the conductive plates, d is the distanceseparating the two capacitor plates, and K is the dielectric constant ofthe dielectric material that fills the space between the two plates.Therefore, in order to provide a capacitor having higher capacitance,either the dielectric constant must be increased, the distance betweenplates made smaller, or the area of capacitor plates be enlarged.

Increasing the dielectric constant of a plate capacitor is difficult todo because it requires replacing the dielectric material with adifferent dielectric material that has a higher dielectric constant. Thenew material has to be integrated into a processing scheme, whichrequires that it be compatible with the materials used as the conductiveplates and electrodes of the capacitor, and be capable of undergoing allof the particular processing that the capacitor structure ordinarilyundergoes. Decreasing the separating distance d between plates is alsoproblematic because that too is a matter which is largely determined bythe choice, in a particular capacitor fabrication process, of theparticular dielectric material, in view of its behavior duringdeposition, and any processing and design tolerances which are necessaryto ensure reliable operation after manufacture.

In an electrolytic capacitor, there is even less control over thedielectric material that is used and its thickness. As illustrated inFIG. 1B, an electrolytic capacitor includes conductive plate 3 which isseparated from an electrolyte fluid 4 by a capacitor dielectric 5. Theelectrolyte fluid is placed in a conductive vessel 6, to which anexternal terminal of the capacitor is connected. Thus, electrolyticcapacitors have only one conductive plate. In some electrolyticcapacitors, a native oxide forms to a final thickness when the plate isplaced in the electrolyte, the native oxide functioning as of acapacitor dielectric. In such cases, the choice of dielectric materialand its thickness are entirely determined by the choice of metal for theconductive plate.

Since the above difficulties prevent the capacitance of a capacitor frombeing increased by choice of dielectric materials and/or change in theplate-separating distance d, it follows that a more effective way toincrease capacitance is to increase the surface area available to thecapacitor as a plate.

SUMMARY OF THE INVENTION

According to an aspect of the invention, a method is provided for makinga capacitor structure having an enhanced plate surface area. The methodincludes providing a mandrel including a major surface having an arrayof features including at least one of: a plurality of first featuresprotruding upward or a plurality of second features extending downwardfrom the major surface. A conformal first conductive layer is formedover the mandrel which conforms to contours of the major surface. Aconformal capacitor dielectric layer is formed over the first conductivelayer. When the capacitor is an electrolytic capacitor, the dielectriclayer can be formed as a native oxide of the conformal first conductivelayer. Alternatively, a dielectric material other than a native oxide ofthe first conductive layer can be deposited. To form an electrolyticcapacitor, the structure including the first conductive layer and thecapacitor dielectric layer is contacted by an electrolyte containedwithin a vessel.

When it is desired to form a plate capacitor, a second conductive layeris formed over the conformal capacitor dielectric layer. In such manner,a capacitor is formed which includes a first plate comprising theconformal first conductive layer, a capacitor dielectric comprising theconformal capacitor dielectric layer, and a second plate comprising thesecond conductive layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a perspective drawing illustrating a simple prior art platecapacitor.

FIG. 1B is a diagram illustrating a simple prior art electrolyticcapacitor.

FIG. 2A is a perspective drawing illustrating an enhanced surface areacapacitor structure according to a first embodiment of the invention.

FIG. 2B is a diagram illustrating exemplary shapes to which features ofan enhanced surface area capacitor may be formed.

FIG. 2C is a perspective drawing illustrating an enhanced surface areacapacitor structure according to a second embodiment of the invention.

FIG. 3 is a perspective drawing illustrating an enhanced surface areacapacitor structure according to a third embodiment of the invention.

FIGS. 4A and 4B are a perspective drawing, and a top-down view,respectively, illustrating an enhanced surface area capacitor structureaccording to a fourth embodiment of the invention.

FIGS. 5A and 5B are a perspective drawing, and a top-down view,respectively, illustrating an enhanced surface area capacitor structureaccording to a fifth embodiment of the invention.

FIGS. 6 through 9B are cross-sectional drawings illustrating steps in amethod for fabricating a mandrel or a capacitor base having enhancedsurface area, as a tool that may be used in fabricating an enhancedsurface area capacitor according to a first method embodiment of theinvention.

FIGS. 10 through 12 are cross-sectional drawings illustrating steps in amethod of fabricating an enhanced surface area capacitor according to afirst method embodiment of the invention.

FIGS. 13 and 14 are cross-sectional drawings illustrating steps to beperformed, subsequent to those illustrated in FIGS. 6 through 12,according to an alternative method embodiment of the invention.

FIGS. 15 through 18 are cross-sectional drawings illustrating steps in amethod of fabricating an enhanced surface area capacitor according to asecond method embodiment of the invention.

FIG. 19 is a cross-sectional drawing illustrating steps performed,subsequent to those illustrated in FIGS. 15 through 18, according to analternative method embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Accordingly, a capacitor having an enhanced surface area, and a methodfor making the same are provided by the present invention. These aredescribed in the embodiments provided herein as follows.

FIG. 2A illustrates a first embodiment of a capacitor structure 10 inwhich at least one plate of the capacitor has a surface provided with anm by n array 11 of upwardly extending features 12. Preferably, thefeatures have conical shape and a high ratio of height to cross-section(aspect ratio). By providing a large number of closely packed verticallyextending features in a small area, great increases, e.g. up to 100 foldor more in surface area can be obtained. As shown in FIG. 2A, capacitor10 includes a base 14 having a surface including an m by n array ofupwardly extending features 12. A first conformal conductive layer 16and a capacitor dielectric layer 18 are placed over the surface andfeatures of the base 14.

When the capacitor is an electrolytic capacitor, such structureincluding base 14, the plate formed by the first conformal conductivelayer 16 and the capacitor dielectric layer 18 are placed in anelectrolyte contained in a vessel, with the plate 16 forming the anode(higher voltage side) of the capacitor, and the electrolytic solutionforming the cathode which has a conductive path to a lower voltage orground through the vessel. Electrolytic capacitors provide largecapacitance only when they remain connected in such way, with the metalcapacitor plate 16 always at a higher voltage than the anode, in whichcase the direction of current flow remains essentially the same.

If the circuit calls for voltages on the capacitor terminals to switchbetween positive and negative values, however, a plate capacitor isneeded, because the electrolytic capacitor would be damaged by anegative voltage from the anode to the cathode. When the capacitor is aplate capacitor, which is formed by two essentially parallel plateshaving a dielectric layer between them, a second conductive layer 20 isformed over the capacitor dielectric layer 18. As an option, one or moreadditional capacitor dielectric layers (not shown) and one or moreadditional conductive layers may be formed, respectively, over secondconductive layer 20, to form a multiple layer capacitor structure. Inthe description of the invention to follow, frequent reference will bemade to plate capacitors, with the understanding, however, thatelectrolytic capacitors are formed by similar processes, the differenceshaving been indicated above.

In the particular embodiment shown in FIG. 2A, a plurality of upwardlyextending features 21 in the shape of pyramidal or conical frustums areprovided in an m by n array in which the numbers m and n are the same.The numbers m and n of features, which define the size of the array offeatures, are both greater than or equal to two. Many different arraysizes and shapes can be implemented by varying the value of m and n.

Moreover, the features are not limited to a particular shape. In theembodiment shown in FIG. 2A, features 12 have the shape of pyramidal orconical frustums (sections of pyramids or cones that lie between twoplanes) However, as indicated by the exemplary shapes set forth in FIG.2B, many shapes are available for the fabrication of features 12. Suchshapes are provided only as examples for fabricating features 12. Theshapes with which features 12 are formed are by no means limited tothese examples.

Generally, surfaces of revolution about an axis provide appropriateshapes for features 12, as well as do polyhedrons which approximate suchsurfaces of revolution, or which are otherwise processed, preferably,such that sharp corners are rounded somewhat at the junction between theplanar surfaces of a polyhedron. An example of a surface of revolutionabout an axis is a paraboloid of revolution 202. Other examples ofshapes of features 12 include a spheroidal cap 204, which may either beprolate (as shown here) or oblate. Other somewhat similar shapes are aspherical cap (not shown) such as a hemisphere, which is similar to thespheroidal cap except that it has uniform radius in every direction, anellipsoidal cap 205, and a spherical segment 206, which is the portionof a sphere lying between two planes. In other examples, the shapes 207,208 are formed by adding spherical caps or spherical segments to thetops of conical or pyramidal frustums that are described above withreference to FIG. 2A. As another example, cones having very low height,or frustums in which the radius decreases rapidly with height, could beformed on top of the frustums found in lower portions of shapes 207,208. Another example of a shape useful for forming features 12 is anelliptic conical frustum 210, which may or may not be formed with a cap,such as an ellipsoidal cap. As another example, an elliptic pyramidalfrustum 212 is shown, which may or may not be formed with an ellipsoidalcap. As also shown in a top-down view in FIG. 2B, a feature 214 havingelongated straight sides may be provided with surfaces 216 of partialrevolution or semi-revolution about an axis, for example, segments offrustums, at its ends, while surfaces 218 on the sides of the feature214 remain essentially trapezoidal. This description of shapes forforming features 12 is provided by way of illustration, and is by nomeans exhaustive.

However, if the features include corners having sharp radii, forexample, when they are rectangular in cross-section, the corners of eachfeature should be rounded, rather than remain at an abrupt angle, toavoid locally high electric fields in the corners, which could causebreakdown and failure of the capacitor dielectric layer.Electropolishing can be used to round sharp corners of features. Manyother array shapes can be implemented, and the features need not extendupwardly, but rather, can extend downwardly from the surface of the base14. A few such alternative embodiments are illustrated in FIGS. 2Cthrough 5.

FIG. 2C illustrates an embodiment of the invention in which a capacitoris formed having a base 24 that includes an m by n array 25 of features26 which extend downwardly from the surface of the base 24. Downwardlyextending features 26 are, thus, depressions in the surface 33 of thebase 24. Such depressions can be generally cylindrical in cross-sectionwhere they meet with the exterior surface 33 of the base 24. Many othershapes are possible, examples of which are provided in FIG. 2B, suchshapes being inverted to define the shapes of depressions 26. As anexample, depressions 26 can have oblong or generally rectangularcross-section where they meet with the surface 33 of the base 24.However, if the depressions 26 are generally rectangular incross-section, the corners of each rectangular depression should berounded, rather than at an abrupt angle, to avoid locally high electricfields in the corners, which could cause breakdown and failure of thecapacitor dielectric layer. As in the embodiment shown in FIG. 2A, in aplate capacitor embodiment, a first conformal conductive layer 28, acapacitor dielectric layer 30, and a second conductive layer 32 areformed over the base 24 having the m by n array 25 of features 26. As inthe embodiment described above relative to FIG. 2A, the numbers m and nof features, which define the size of the array of features, are bothgreater than or equal to two, and additional capacitor dielectriclayer(s) and additional conductive layer(s) can be formed over thesecond conductive layer 32 to form a multiple layer capacitor structure,if desired.

FIG. 3 illustrates another embodiment of the invention, in which acapacitor includes a base 34 having an m by n array 35 of features, inwhich some features 36 a extend upwardly, and other features 36 b extenddownwardly, as depressions in the surface of the base 34. As in theembodiment shown in FIG. 2A in a plate capacitor embodiment, a firstconformal conductive layer 38, a capacitor dielectric layer 40, and asecond conductive layer 42 are formed over the base 34 having the m by narray 35 of features 36. Additional capacitor dielectric layer(s) andconductive layer(s) can be provided over the second conductive layer 42to form a multiple layer capacitor, if desired. As in the embodimentdescribed above relative to FIG. 2A, the numbers m and n of features,which define the size of the array of features, are both greater than orequal to two.

FIGS. 4A and 4B are a perspective drawing, and a top-down view,respectively, illustrating another embodiment of the invention in whicha plate capacitor 43 is formed having a base 44 which includes an m by narray 45 (FIG. 4B) of features 46 in the shape of ridges which extendupwardly from the surface 41 of the base 44. The ridge-shaped features46 can be elongated, as shown in FIGS. 4A and 4B, and generally parallelin orientation, for ease of fabrication and to pack a large number ofridges into an allotted space. As shown in FIG. 4A, the ridges 46 arepreferably smooth and rounded in shape, for example, sinusoidal inshape, rather than having rectilinear corners and edges betweensurfaces, to avoid locally high electric fields arising at such cornerswhich could cause breakdown and early failure of the capacitordielectric layer. As in the embodiment shown in FIG. 2A, in a platecapacitor embodiment, a first conformal conductive layer 48, a capacitordielectric layer 50, and a second conductive layer 52 are formed overthe base 44 having the m by n array 45 of ridge-shaped features 46 andadditional capacitor dielectric layer(s) and conductive layer(s) can beprovided to form a multiple layer capacitor, if desired. As in theembodiment described above relative to FIG. 2A, the numbers m and n offeatures, which define the size of the array of features, are bothgreater than or equal to two.

FIGS. 5A and 5B are a perspective drawing, and a top-down view,respectively, illustrating another embodiment of the invention in whicha capacitor 53 is formed having a base 54 which includes an m by n array55 of features 56 in the shape of troughs which extend downwardly fromthe surface 51 of the base 54. The trough-shaped features 56 can beelongated, as shown in FIGS. 5A and 5B, and are preferably generallyparallel in orientation, for ease of fabrication and to maximize thenumber of troughs packed into the allotted space. As shown in FIG. 5A,the troughs 56 are preferably smooth and rounded in shape, rather thanhaving rectilinear corners and edges between surfaces, to avoid locallyhigh electric fields arising at such corners, which could causebreakdown and failure of the capacitor dielectric layer. As in theembodiment shown in FIG. 2A, in a plate capacitor embodiment, a firstconformal conductive layer 58, a capacitor dielectric layer 60, and asecond conductive layer 62 are formed over the base 54 having the m by narray 55 of trough-shaped features 56. As in the embodiment describedabove relative to FIG. 2A, the numbers m and n of features, which definethe size of the array of features, are both greater than or equal totwo.

Next, a first method embodiment of fabricating a capacitor according toany of the above-described structural embodiments is described,referring to FIGS. 6 through 14. In this embodiment, a capacitor isformed on the surface of a mandrel, which is preferably reusable, suchthat after the capacitor is fully formed, it is then removed from themandrel, and the mandrel is then free to be used in fabricating anothercapacitor. The description of fabricating a capacitor according to thisembodiment begins by describing the way in which a reusable mandrel isfabricated.

As shown in FIG. 6, a generally planar substrate 100 is provided, whichis shaped, through processing, into a mandrel upon which a capacitorwill be formed. In an embodiment, substrate 100 can be formed of asingle crystal semiconductor or, alternatively, polycrystallinesemiconductor, for which processes are well-developed forphotolithographic patterning and anisotropic, directional etching tosmall dimensions. Alternatively, substrate 100 can be formed of anymaterial which permits anisotropic, directional etching, or machining tothe dimensions required to produce the feature shapes and sizes toobtain the required capacitance. Preferably, a mandrel is formed byetching a single crystal silicon or polycrystalline silicon(“polysilicon”) substrate 100.

As shown in FIG. 7, a mask layer 110 is deposited over substrate 100,and then patterned, using photolithography, and/or one or more etchingprocesses, to create a set of mask patterns 112 over the surface ofsubstrate 100, as shown in FIG. 8. In a preferred embodiment in whichsubstrate 100 comprises single crystal silicon or polysilicon, masklayer 110 can include a photoresist material; however, mask layer 110preferably comprises a hardmask including one or more materials selectedfrom the following: silicon nitride, silicon oxide, doped silicate glassincluding one or more of borosilicate glass (BSG), phosphosilicate glass(PSG), and borophosphosilicate glass (BPSG), such that anisotropic,vertical etching can be performed with a process such as reactive ionetch (RIE), while the hardmask patterns 112 sufficiently remainthroughout the etching process.

Next, as shown in FIG. 9A, the substrate 100 is etched anisotropicallyin the vertical direction, selective to the material of the maskpatterns 112, to define protrusions 114 which extend above the surface116 of the substrate 100. If the protrusions are not sufficientlyrounded after the anisotropic etching process, various other processessuch as a controlled isotropic etch, and/or electropolishing can be usedto provide rounding. For best results, an anisotropic etch process isselected in which material is etched primarily perpendicular to theplane of the substrate 100; i.e., vertically. Although etching iscarried out primarily in the vertical direction, the direction of theetch process is preferably not entirely vertical, such that sidewalls118 of the protrusions 114 are somewhat sloped, and some rounding isachieved where the protrusions 114 meet the surface 116 of the substrate100. An isotropic etch process, in which etching is uniform in alldirections, is not preferred for this step because it would result inshorter protrusions 114, and possible undercut of the material of thesubstrate 100 under mask patterns 112, resulting in a poorly controlledprocess. When the substrate 100 is formed of silicon and a hardmask isused, composed of one or more of the above-noted materials, ananisotropic vertical etch process can be realized by any one of manywell-known reactive ion etching (RIE) processes.

Thereafter, as shown in FIG. 9B, an etch or cleaning process isperformed to remove any material of the mask patterns 112 remainingafter etching substrate 100, thus determining the shape of a mandrelstructure 120, as shown. The mandrel structure 120 now defines the shapeof a surface for forming a capacitor structure, as will be described inthe following, with reference to FIGS. 10-18. In the embodimentsdescribed below, the mandrel structure 120, formed as described aboverelative to FIGS. 6 through 9A, can be used as the surface itself uponwhich a capacitor is formed. Alternatively, a mold can be made frommandrel 120 to form a like-shaped mandrel, on which a capacitorstructure is then formed. The like-shaped mandrel can thus be formed ofa low-cost material such as a polymeric material. In the descriptionwhich follows, mandrel 120 shall refer to either an original mandrel120, formed by the above process described relative to FIGS. 6 through9B, or a like-shaped mandrel formed by a mold of mandrel 120. Also atthis time, mandrel 120 can be metallized and/or treated at a top surfacewith a low-adhesion material such as chromium, ruthenium, molybdenumstainless steel or heavily doped polysilicon to facilitate the laterremoval of materials deposited thereover.

The formation of a capacitor structure according to a first methodembodiment, using mandrel 120, is now described with reference to FIGS.10-14. As shown in FIG. 10, a first conformal conductive layer 122 isformed over the surface 116 of the mandrel 120, including protrusions114. If a low adhesion material layer has not already been formed onmandrel 120, the first conductive layer 122 preferably includes a lowadhesion material such as chromium, ruthenium, molybdenum stainlesssteel or heavily doped polysilicon in contact with the mandrel 120, tohelp facilitate later removal of the capacitor structure from themandrel 120. Such low adhesion material is deposited to form a layer incontact with mandrel 120, preferably by any one of several conventionalprocesses for chemical vapor deposition (CVD) or by sputtering,including room temperature sputtering. When it is not necessary toremove the capacitor from mandrel 120 after formation, such as when alow-cost like-shaped mandrel is used, formed from a mold of the originalmandrel 120, the low adhesion material can be omitted. In either case,the first conductive layer 122 preferably includes an additional surfaceconductive material conformally deposited by any one of many availableconventional techniques onto the low adhesion material layer, or ontothe mandrel 120. Examples of such surface conductive material includebut are not limited to copper, nickel, aluminum, tantalum, niobium,magnesium, titanium, tungsten, zirconium, and/or zinc, low-resistancecompounds of metals, and heavily doped polysilicon.

Next, as shown in FIG. 11, a capacitor dielectric layer 124 is formed.Such capacitor dielectric layer 124 is preferably formed of a materialwhich conforms to the surface shape of the first conductive layer 122 onwhich it is deposited, has a preferably high dielectric constant k, andis compatible with the materials used in the conductive layers of thecapacitor structure which it contacts. Preferred materials for thecapacitor dielectric layer 124 include native oxides of the surfacemetal of the conformal first conductive layer 122, silicon dioxide,silicon nitride, and silicon oxynitride, and combinations of layers ofsuch materials. Native oxides of the first conductive layer 122 formupon exposure to oxygen when particular metals are used therein,including but not limited to aluminum, magnesium, tantalum, titanium,niobium, zinc, and zirconium. Such process can be accelerated, ifdesired, by baking the structure in an oxygen atmosphere.

In a particular embodiment, an electrolytic capacitor having enhancedsurface area is formed by a structure of the conformal first conductivelayer 122, covered by a capacitor dielectric layer 124, and supported bya mandrel or like-shaped mandrel 120, when that structure is contactedwith an electrolyte, for example, an aqueous buffered acidic solution ina vessel, similar to the arrangement shown in FIG. 1B, except for theuse of the enhanced surface area structure of layers 120, 122 and 124.In such embodiment, the capacitor dielectric layer 124 can be formed asa native oxide of the surface metal of the conformal first conductivelayer 122, either before or after the structure is contacted with theelectrolyte.

To form a plate capacitor rather than an electrolytic capacitor,additional processing is needed. As shown in FIG. 12, a secondconductive layer 126 is formed over the capacitor dielectric layer 124to form a layered stack including the conformal first conductive layer122, capacitor dielectric layer 124, and second conductive materiallayer 126. The formation of second conductive material layer 126 canvary depending upon subsequent steps employed in the formation of aplate capacitor. For example, it may be desired to fabricate a capacitorhaving multiple capacitor dielectric layers and a corresponding numberof conductive layers, in order to increase the total surface area of thecapacitor. In such case, second conductive material layer 126 ispreferably deposited conformally over capacitor dielectric layer 124,such that an exposed surface 127 of second conductive material layer 124has increased surface area by conforming generally to the contours ofcapacitor dielectric layer 124. Thereafter, subsequent depositions of anadditional capacitor dielectric layer (not shown) and an additionalsecond conductive material layer (not shown) are performed to provide acapacitor stack having a plurality of capacitor dielectric layers, eachdielectric layer being located between respective pairs of conductivelayers.

However, when the capacitor is to be formed with a single capacitordielectric layer 124, the second conductive layer 126 need not bedeposited conformally, since the top surface 127 will not be usedthereafter as a surface which determines the surface area of asubsequently deposited capacitor dielectric layer. In such case, thetypes of processes available for forming the second conductive layer 126can be greater than those available for forming the conformal firstconductive layer 122.

Depending on whether a reusable mandrel 120, formed by processesdescribed above with reference to FIGS. 6 through 9A, has been used as asurface for fabricating the layered capacitor stack structure 128, orwhether layered capacitor stack 128 is formed on a mandrel 120 as a basedesigned to remain attached thereto, fabrication now proceeds accordingto one of several ways. If a reusable mandrel 120 has been used, processsteps are now needed to form a base to which the layered capacitor stack128 is to adhere, at which time mandrel 120 is removed from the layeredcapacitor stack 128. As shown in FIG. 13, a base 130 is then formed oversecond conductive layer 126, such that layered capacitor stack 128 isnow attached to base 130. After the base 130 is formed, mandrel 120 isremoved, as shown in FIG. 14, leaving the layered capacitor stack 128attached to base 130. The removal of mandrel 120 is possible because ofthe low adhesion material layer formed earlier on the contact surfacebetween mandrel 120 and the metal deposited to form the conformal firstconductive layer 122.

However, if the layered capacitor stack 128 has been formed on a base120 designed to remain attached, then only electrodes remain to beformed and connected to the plates of the capacitor provided by thefirst conductive layer 122 and the second conductive layer 126 of thelayered capacitor stack 128. In either case, the base 130 can be formedby deposition of any one of several materials including dielectricmaterials, such as organic origin dielectrics among which are thosecategorized as having low dielectric constants known as “low-k”dielectrics such as polyimide and various other polymers. A preferredmaterial for the base 120 is epoxy. Alternatively, inorganic dielectricmaterials can be used, such as silicon oxide, silicon nitride, siliconoxynitride, for example, which can be formed by any of severalwell-known methods, including chemical, vapor, plasma, andplasma-enhanced deposition and “spin-on” methods, e.g., forspin-on-glass, followed by subsequent hardening processes.Alternatively, the base 130, being attached to one plate of thecapacitor formed by second conductive layer 126, can be formed ofconductive material, depending upon the application to which thecapacitor is employed. For example, if second conductive layer 126 is tobe held at ground potential, base 130, to which it is attached, can beexternally grounded. When the base 130 is formed of a conductivematerial, the capacitor structure can be insulated from unwantedelectrical interaction by an insulator layer formed over parts of thebase 130 and other exposed conductive elements.

While the above-described embodiment of a method of forming a capacitoris provided using a mandrel 120 having a surface including a pluralityof protrusions, FIGS. 15 through 18 illustrate an alternative embodimentof the invention in which a capacitor is fabricated by forming a layeredstack over a surface of a mandrel (or base) 150 having a plurality ofdepressions 152. Further, the above-described method embodiment can becombined with the method embodiment herein in a method in which amandrel or base having both protrusions and depressions provides asurface upon which a capacitor structure is formed.

As shown in FIG. 16, a conformal first conductive layer 154 is depositedover the mandrel or base 150. Thereafter, as shown in FIG. 17, acapacitor dielectric layer 156 is formed over the conformal firstconductive layer 154. When it is desired to form an electrolyticcapacitor, the structure including base 150, conformal first conductivelayer 154 and capacitor dielectric layer 156 are then placed in contactwith an electrolyte contained in a vessel to form the electrolyticcapacitor. However, when it is desired to form a plate capacitor, then,as shown in FIG. 18, a second conductive layer 158 is deposited to forma layered plate capacitor stack 160 including the conformal firstconductive layer 154, capacitor dielectric layer 156, and secondconductive layer 158. At this point, processing is similar to the methoddescribed above with reference to FIGS. 12, 13 and 14.

Depending on whether a reusable mandrel 150, formed by processesdescribed above with reference to FIGS. 6 through 9A, has been used as asurface for fabricating the layered capacitor stack structure 160, or abase 150 designed to remain attached is used, fabrication now proceedsaccording to one of several ways. If a reusable mandrel 150 has beenused, process steps are now needed to form a base to which the layeredcapacitor stack 160 is to adhere, while mandrel 150 is removed from thelayered capacitor stack 160. As shown in FIG. 19, a base 170 is formedover second conductive layer 158 such that layered capacitor stack 160is now attached to base 170. After the base 170 is formed, mandrel 150is removed, as shown in FIG. 19, leaving the layered capacitor stack 160attached to base 170.

However, if the layered capacitor stack 160 has been formed on a base150 designed to remain attached, then the capacitor formation process iscomplete, except only for electrodes (not shown) which remain to beformed and connected to the plates of the capacitor provided by thefirst conductive layer 154 and the second conductive layer 158 of thelayered capacitor stack 160.

Thus, embodiments of enhanced surface area capacitor structures andmethods of making them are provided and described herein. Such capacitorstructures and methods meet the requirements for capacitors of largecapacitance and smaller size of today's microelectronics industries.

As these and other variations and combinations of the features discussedabove can be utilized, the foregoing description of the preferredembodiments should be taken by way of illustration, rather than by wayof limitation of the invention, as defined by the claims.

1. A method of making a capacitor structure having an enhanced platesurface area, comprising: providing a mandrel having a major surfaceextending in a first direction and in a second direction crossing saidfirst direction, said major surface having an array of featuresincluding at least one of: a plurality of first features protrudingupward from said major surface or a plurality of second featuresprotruding downward from said major surface, said array including atleast two of said features aligned in said first direction and at leasttwo of said features aligned in said second direction, each of at leastsome of said features having a predetermined first shape and having apredetermined first width in said first direction and a predeterminedfirst length in said second direction; forming a conformal firstconductive layer over said mandrel, said first conductive layerconforming to contours of said major surface; and forming a conformalcapacitor dielectric layer over said conformal first conductive layer.2. The method of claim 1, further comprising contacting said capacitorstructure including said mandrel, said conformal first conductive layer,and said conformal capacitor dielectric layer with an electrolyte toform an electrolytic capacitor.
 3. The method of claim 1, furthercomprising forming a second conductive layer over said conformalcapacitor dielectric layer to form a plate capacitor including: a) afirst plate, said first plate including said conformal first conductivelayer, b) a capacitor dielectric including said conformal capacitordielectric layer, and c) a second plate including said second conductivelayer.
 4. The method of claim 3, further comprising forming a base ofsaid plate capacitor in contact with said second conductive layer. 5.The method of claim 4, further comprising detaching said mandrel fromsaid conformal first conductive layer, while said plate capacitorremains attached to said base.
 6. The method of claim 5, furthercomprising reusing said mandrel to form an additional plate capacitorafter said step of detaching said mandrel.
 7. The method of claim 1,wherein said array of features includes said first features.
 8. Themethod of claim 1, wherein said array of features includes said secondfeatures.
 9. The method of claim 1, wherein said array of featuresincludes both said first features and said second features.
 10. Themethod of claim 1, wherein at least some of said first features havesubstantially conical shape.
 11. The method of claim 1, wherein at leastsome of said features have ridge shape.
 12. The method of claim 11,wherein said ridge-shaped first features of said mandrel are elongatedand oriented in parallel.
 13. The method of claim 1, wherein at leastsome of said second features of said mandrel have trough shape.
 14. Themethod of claim 13, wherein said trough-shaped second features of saidmandrel are elongated and oriented in parallel.
 15. The method of claim1, wherein said step of forming said conformal first conductive layerincludes forming a conformal low adhesion layer in contact with saidmandrel, said conformal low adhesion layer including at least one ofchromium, ruthenium, molybdenum, stainless steel and heavily dopedpolysilicon, said conformal low adhesion layer facilitating removal ofsaid mandrel from said conformal first conductive layer.
 16. The methodof claim 1, wherein said step of forming said conformal first conductivelayer includes depositing at least one material selected from the groupconsisting of metal, a low-resistance compound of a metal and heavilydoped polysilicon.
 17. The method of claim 16, wherein said metalincludes at least one selected from the group consisting of copper,nickel, aluminum, magnesium, niobium, tantalum, titanium, tungsten,zirconium and zinc.
 18. The method of claim 1, wherein said conformalcapacitor dielectric layer includes at least one of silicon oxide,silicon nitride and silicon oxynitride.
 19. The method of claim 4,wherein said base comprises a material including epoxy.
 20. The methodof claim 4, further comprising performing the following steps in orderone or more times prior to forming said base, to form one or moreadditional plates of said plate capacitor: forming an additionalcapacitor dielectric layer over said second conductive layer; andforming an additional second conductive layer over said additionalcapacitor dielectric layer.